Hierarchical strategies for efficient fault recovery on the reconfigurable PAnDA device

Trefzer, Martin A.; Lawson, David M. R.; Bale, Simon J.; Walker, James A.; Tyrrell, Andy M.; Lawson, David M.R.; Lawson, David; Walker, James; Bale, Simon; Trefzer, Martin; Tyrrell, Andy

Abstract

A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure.

Citation

Trefzer, M. A., Lawson, D. M. R., Bale, S. J., Walker, J. A., Tyrrell, A. M., Lawson, D. M., Lawson, D., Walker, J., Bale, S., Trefzer, M., & Tyrrell, A. (2017). Hierarchical strategies for efficient fault recovery on the reconfigurable PAnDA device. IEEE Transactions on Computers, 66(6), 930-945. https://doi.org/10.1109/TC.2016.2632722

• Acceptance Date: Nov 21, 2016
• Publication Date: Jun 1, 2017
• Deposit Date: Feb 13, 2017
• Publicly Available Date: Jun 1, 2017
• Journal: IEEE transactions on computers
• Electronic ISSN: 0018-9340
• Publisher: Institute of Electrical and Electronics Engineers
• Peer Reviewed: Peer Reviewed
• Volume: 66
• Issue: 6
• Pages: 930-945
• DOI: https://doi.org/10.1109/TC.2016.2632722
• Keywords: Circuit faults, Computer architecture, Routing, Field programmable gate arrays, Maintenance engineering, Transistors, Fabrics
• Public URL: https://hull-repository.worktribe.com/output/448036
• Publisher URL: http://ieeexplore.ieee.org/document/7756359/
• Additional Information: This is the authors' accepted manuscript of an article which has been accepted for future publication in: IEEE transactions on computers.
• Contract Date: Feb 13, 2017